Doping of Semiconductors

Doping of Semiconductors

The evolution of the transistor architecture from planar to non-planar combined with its continued miniaturisation has created the need for conformal and damage free doping (Figure 1).  As device size approaches 10 nm and below it will be necessary to take this a step further and deterministically dope the materials from which they are fabricated.  Ion implantation (Figure 2 (a)), the standard industrial method for doping semiconductors, involves bombarding the surface of the material with highly energetic ions of choice (e.g. phosphorus or boron).

Fig 1 doping

Though it allows excellent control over the dose and depth of the ions in the semiconductor, this high energy process amorphises the crystal structure and requires high temperature annealing to recrystallise and activate the dopant atoms in-situ.  This has worked perfectly for devices with planar architectures however the unidirectional nature of the ion beam is not so effective for non-planar devices.  Molecular layer doping (Figure 2(b) (MLD), which involves the diffusion of dopant atoms into the semiconductor from surface bound molecules, has been identified as a conformal and non-destructive method required for sub-10 nm technologies.

Fig 2 doping

Molecular Layer Doping

Recently MLD on Ge has been demonstrated by MCAG researchers.  MCAG have also demonstrated high doping levels in Si achieved by MLD.  Although based primarily in the Chemistry Department in UCC, MCAG has unlimited access to state of the art facilities across UCC, Tyndall National Institute in Cork and CRANN in Trinity College Dublin for producing and characterising doped materials.

Arsenic is a suitable candidate for heavy and ultra-shallow n-doping of silicon.  We have shown controlled monolayer doping (MLD) of bulk and nanostructured crystalline silicon with As at concentrations approaching 2 × 1020 atoms cm–3. Characterisation of doped structures after the MLD process confirmed that they remained defect- and damage-free, with no indication of increased roughness or a change in morphology. Electrical characterisation of the doped substrates and nanowire test structures allowed determination of resistivity, sheet resistance, and active doping levels. Extremely high As-doped Si substrates and nanowire devices could be obtained and controlled using specific capping and annealing steps. Significantly, the As-doped nanowires exhibited resistances several orders of magnitude lower than the predoped materials. (ACS Applied Materials and Interfaces 2015 10.1021/acsami.5b03768)

The functionalisation of planar silicon with arsenic- and phosphorus-based azides was investigated. Covalently bonded and well-ordered alkyne-terminated monolayers were prepared from a range of commercially available dialkyne precursors using a well-known thermal hydrosilylation mechanism to form an acetylene-terminated monolayer. The terminal acetylene moieties were further functionalised through the application of copper-catalysed azide–alkyne cycloaddition (CuAAC) reactions between dopant-containing azides and the terminal acetylene groups. The introduction of dopant molecules via this method does not require harsh conditions typically employed in traditional monolayer doping approaches, enabling greater surface coverage with improved resistance toward reoxidation. X-ray photoelectron spectroscopy studies showed successful dialkyne incorporation with minimal Si surface oxidation, and monitoring of the C 1s and N 1s core-level spectra showed successful azide–alkyne cycloaddition. Electrochemical capacitance–voltage measurements showed effective diffusion of the activated dopant atoms into the Si substrates. (ACS Applied Materials and Interfaces 2016, 10.1021/acsami.5b11731)


Electrical Characterisation

In Tyndall there are a plethora of probe stations capable of extracting I-V data.  Many of these include temperature control which allows you to heat substrates up to 373 K and down to 4 K.

Selected Publications

Long, B. Holmes, J. D.; Duffy, R.  ‘Process for molecular layer doping of substrates’  Initial US Patent filed 16 February 2015.  US Patent Number: US62/116,877.

Duffy, R.; Shayesteh, M.; Thomas, K.; Pelucchi, E.; Yu, R.; Gangnaik, A.; Georgiev, Y. M.; Carolan, P.; Petkov, N.; Long, B. Holmes, J. D.  ‘Access resistance reduction in Ge nanowires and substrates based on non-destructive gas-source dopant in-diffusion’  J. Mater. Chem. C  2014, 2 (43), 9248-9257.